Skip to Main content Skip to Navigation
Conference papers

Analog Duty Cycle Controller Using Backgate Body Biasing For 5G Millimeter Wave Applications

Abstract : This work presents the first 21-43 GHz CMOS analog Duty Cycle Controller (DCC) implemented in 28 nm FDSOI. The main application is millimeter wave mixers with CMOS digital signals. The proposed circuit corrects the input duty cycle with a negative feedback analog loop. Observability of the duty cycle is made through a passive low pass filter and the control is achieved by modifying the rise and fall time of the input clock signal, via backgate biasing of an inverter chain. The circuit has been validated by post layout, Monte-Carlo and corner simulations. At 28 GHz, the duty cycle correction range varies from 40 % to 55 %, and the additional power consumption introduced by the correction loop is frequency independent and is equal to 0.6 mW.
Document type :
Conference papers
Complete list of metadata
Contributor : Antoine Frappé Connect in order to contact the contributor
Submitted on : Thursday, January 6, 2022 - 3:17:06 PM
Last modification on : Tuesday, May 17, 2022 - 1:28:45 PM
Long-term archiving on: : Thursday, April 7, 2022 - 7:36:55 PM


Files produced by the author(s)



Clément Beauquier, David Duperray, Chadi Jabbour, Patricia Desgreys, Antoine Frappé, et al.. Analog Duty Cycle Controller Using Backgate Body Biasing For 5G Millimeter Wave Applications. 28th IEEE International Conference on Electronics Circuits and Systems, ICECS 2021, Nov 2021, Dubai, United Arab Emirates. ⟨10.1109/ICECS53924.2021.9665600⟩. ⟨hal-03515052⟩



Record views


Files downloads