G. A. Pratt, Distributed synchronous clocking, IEEE Transactions on Parallel and Distributed Systems, vol.6, issue.3, pp.314-328, 1995.
DOI : 10.1109/71.372779

E. Zianbetov, All-digital PLL array provides reliable distributed clock for SOCs, IEEE international ISCAS conf, pp.2589-2593, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00655799

E. Zianbetov, Design and VHDL modeling of all-digital PLLs, 8 th IEEE international NEWCAS conf, pp.293-296, 2010.

J. A. Thierno, A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI, IEEE Journal of Solid-State Circuits, vol.43, issue.1, 2008.
DOI : 10.1109/JSSC.2007.910966

P. M. Levine, A high-resolutino flash time-to-digital converter and calibration, proceeding of International Test Conference, pp.1148-1157, 2004.