The core clock system on the next generation Itanium1 microprocessor, IEEE International Solid- State Circuits Conference, pp.146-453, 2002. ,
Clock generation for a 32nm server processor with scalable cores, IEEE International Solid-State Circuits Conference, pp.82-83, 2011. ,
FPGA implementation of reconfigurable ADPLL network for distributed clock generation, 2011 International Conference on Field-Programmable Technology, pp.1-4, 2011. ,
DOI : 10.1109/FPT.2011.6132670
URL : https://hal.archives-ouvertes.fr/hal-01053755
Design and VHDL modeling of all-digital PLLs, 8 th IEEE international NEWCAS conf, pp.293-296, 2010. ,
All-digital PLL array provides reliable distributed clock for SOCs, 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp.2589-2592, 2011. ,
DOI : 10.1109/ISCAS.2011.5938134
URL : https://hal.archives-ouvertes.fr/hal-00655799
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI, IEEE Journal of Solid-State Circuits, vol.43, issue.1, 2008. ,
DOI : 10.1109/JSSC.2007.910966
A stream cipher based on linear feedback over GF (2 8 ), Information Security and Privacy, pp.135-146, 1998. ,
A Novel All-Digital PLL With Software Adaptive Filter, IEEE Journal of Solid-State Circuits, vol.39, issue.3, pp.476-483, 2004. ,
DOI : 10.1109/JSSC.2003.822780