A. Abdelhadi, Timing-driven variation-aware nonuniform clock mesh synthesis, Proceedings of the 20th symposium on Great lakes symposium on VLSI, GLSVLSI '10, pp.15-20, 2010.
DOI : 10.1145/1785481.1785487
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.222.8238

V. Tiwari, Reducing power in high-performance microprocessors, Proceedings of the 35th annual conference on Design automation conference , DAC '98, pp.732-737, 1998.
DOI : 10.1145/277044.277227

F. Anceau, A synchronous approach for clocking VLSI systems, Solid-State Circuits, IEEE Journal, vol.17, issue.1, pp.51-56, 1982.

S. Rusu, A 45 nm 8-Core Enterprise Xeon¯ Processor, IEEE Journal of Solid-State Circuits, vol.45, issue.1, pp.7-14, 2010.
DOI : 10.1109/JSSC.2009.2034076

G. A. Pratt, Distributed synchronous clocking, IEEE Transactions on Parallel and Distributed Systems, vol.6, issue.3, pp.314-328, 1995.
DOI : 10.1109/71.372779

M. Maza, . Salim, M. Aranda, and . Linares, Analysis and verification of interconnected rings as clock distribution networks, Proceedins of the 14th ACM Great Lakes symposium on VLSI , GLSVLSI '04, pp.312-315, 2004.
DOI : 10.1145/988952.989027

E. Zianbetov, All-digital PLL array provides reliable distributed clock for SOCs, IEEE international ISCAS conf, pp.2589-2593, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00655799

A. Korniienko, . Scorletti, . Gérard, E. Colinet, E. Blanco et al., Control law synthesis for distributed multi-agent systems: Application to active clock distribution networks, Proceedings of the 2011 American Control Conference, pp.4691-4696, 2011.
DOI : 10.1109/ACC.2011.5991295
URL : https://hal.archives-ouvertes.fr/hal-01181176

. Akre, J. Juillard, D. Galayko, and E. Colinet, Synchronization analysis of networks of self-sampled all-digital phaselocked loops, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.59, issue.4, pp.708-720, 2012.

R. S. Johnson, A Modern Introduction to the Mathematical Theory of Water Waves, 1997.
DOI : 10.1017/CBO9780511624056