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Design and FPGA Implementation of Modular Multiplication Methods Using Cellular Automata Zied Guitouni 941973-0 Roselyne Chotin-Avot c4d9f5dcaae8bde91b430aad20294927 lip6.fr roselyne-chotin-avot 3324 806866-3324 https://www.idref.fr/078439841 https://orcid.org/0000-0001-7990-9070 http://isni.org/isni/0000000140225771 https://viaf.org/viaf/216135094 http://www.researcherid.com/rid/ESK-0289-2022 http://www.researcherid.com/rid/CKE-1524-2022 http://www.researcherid.com/rid/http://www.researcherid.com/rid/ESK-0289-2022 http://www.researcherid.com/rid/http://www.researcherid.com/rid/CKE-1524-2022 Mohsen Machhout 228741-0 Habib Mehrez f23ceb9eb94c548be6bcb2c87854a7f0 lip6.fr habib-mehrez 9743 18199-9743 https://www.idref.fr/089368088 https://orcid.org/0000-0002-0692-1754 Rached Tourki 228743-0 Roselyne Chotin c4d9f5dcaae8bde91b430aad20294927 lip6.fr 2016-02-01 13:41:47 2026-01-12 13:00:03 2016-02-01 13:41:47 2010-03-23 contributor Roselyne Chotin c4d9f5dcaae8bde91b430aad20294927 lip6.fr CCSD hal-01265630 https://hal.sorbonne-universite.fr/hal-01265630 guitouni:hal-01265630 <i>DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology</i>, Mar 2010, Hammamet, Tunisia. pp.1-5, <a target="_blank" href="https://dx.doi.org/10.1109/DTIS.2010.5487586">⟨10.1109/DTIS.2010.5487586⟩</a> DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Mar 2010, Hammamet, Tunisia. pp.1-5, ⟨10.1109/DTIS.2010.5487586⟩ Université Pierre et Marie Curie CNRS - Centre national de la recherche scientifique Laboratoire d'Informatique de Paris 6 UPMC Pôle 1 Circuits Intégrés Numériques et Analogiques Sorbonne Université Faculté des Sciences de Sorbonne Université Alliance Sorbonne Université International No No Yes Yes Design and FPGA Implementation of Modular Multiplication Methods Using Cellular Automata Zied Guitouni 941973-0 Roselyne Chotin-Avot c4d9f5dcaae8bde91b430aad20294927 lip6.fr roselyne-chotin-avot 3324 806866-3324 https://www.idref.fr/078439841 https://orcid.org/0000-0001-7990-9070 http://isni.org/isni/0000000140225771 https://viaf.org/viaf/216135094 http://www.researcherid.com/rid/ESK-0289-2022 http://www.researcherid.com/rid/CKE-1524-2022 http://www.researcherid.com/rid/http://www.researcherid.com/rid/ESK-0289-2022 http://www.researcherid.com/rid/http://www.researcherid.com/rid/CKE-1524-2022 Mohsen Machhout 228741-0 Habib Mehrez f23ceb9eb94c548be6bcb2c87854a7f0 lip6.fr habib-mehrez 9743 18199-9743 https://www.idref.fr/089368088 https://orcid.org/0000-0002-0692-1754 Rached Tourki 228743-0 DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology 2010-03-23 2010-03-25 Hammamet Tunisia IEEE 1-5 2010 10.1109/DTIS.2010.5487586 English Computer Science [cs]/Hardware Architecture [cs.AR] Conference papers Conference papers Conference papers

Cellular automata (CA) have been accepted as a good evolutionary computational model for the simulation of complex physical systems. They have been used for various applications, such as parallel processing computations and number theory. In this paper, we studied the applications of cellular automata for the modular multiplications; we proposed two new architectures of multipliers based on cellular automata over finite field GF(2m). Since they have regularity, modularity and concurrency, they are suitable for VLSI implementation. The proposed architectures can be easily implemented into the hardware design of crypto-coprocessors.

Circuits Intégrés Numériques et Analogiques CIAN 2004-01-01 2017-12-31

Laboratoire d'Electronique et Microélectronique

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http://www.lip6.fr/ https://ror.org/02en5vm52 Université Pierre et Marie Curie - Paris 6 UPMC 2017-12-31

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