F. Qureshi, M. Garrido, and O. Gustafsson, Unified architecture for 2, 3, 4, 5, and 7-point DFTs based on Winograd Fourier transform algorithm, Electronics Letters, vol.49, issue.5, pp.348-349, 2013.
DOI : 10.1049/el.2012.0577

T. Patyk, F. Qureshi, and J. Takala, Hardware-Efficient Twiddle Factor Generator for Mixed Radix-2/3/4/5 FFTs, 2016 IEEE International Workshop on Signal Processing Systems (SiPS), pp.201-206, 2016.
DOI : 10.1109/SiPS.2016.43

J. Chen, J. Hu, S. Lee, and G. E. Sobelman, Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.23, issue.2, pp.221-229, 2015.
DOI : 10.1109/TVLSI.2014.2304834

M. Garrido, A New Representation of FFT Algorithms Using Triangular Matrices, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.63, issue.10, pp.1737-1745, 2016.
DOI : 10.1109/TCSI.2016.2587822

S. J. Huang and S. G. Chen, A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.59, issue.8, pp.1752-1765, 2012.
DOI : 10.1109/TCSI.2011.2180430

M. Garrido, Efficient hardware architectures for the computation of the FFT and other related signal processing algorithms in real time, 2009.

M. Garrido, R. Andersson, F. Qureshi, and O. Gustafsson, Multiplierless Unity-Gain SDF FFTs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, issue.9, pp.3003-3007, 2016.
DOI : 10.1109/TVLSI.2016.2542583

URL : http://liu.diva-portal.org/smash/get/diva2:1046263/FULLTEXT01

M. Garrido, J. Grajal, M. A. Sanchez, and O. Gustafsson, Pipelined Radix-<formula formulatype="inline"><tex Notation="TeX">$2^{k}$</tex></formula> Feedforward FFT Architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.21, issue.1, pp.23-32, 2013.
DOI : 10.1109/TVLSI.2011.2178275

URL : http://oa.upm.es/12291/2/INVE_MEM_2011_110916.pdf

M. Garrido, M. Snchez, M. L. Lpez-vallejo, and J. Grajal, A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.25, issue.1, pp.1-5, 2016.
DOI : 10.1109/TVLSI.2016.2567784

A. Wang, J. Bachrach, and B. Nikoli, A generator of memory-based, runtime-reconfigurable 2 n 3 m 5 k FFT engines, Proc. IEEE Int, pp.1016-1020, 2016.

I. Cho, T. Patyk, D. Guevorkian, J. Takala, and S. Bhattacharyya, Pipelined FFT for wireless communications supporting 128 ? 2048/1536 -point transforms, Proc. IEEE Global Conf. on Signal and Information Process, pp.1242-1245, 2013.
DOI : 10.1109/globalsip.2013.6737133

. Altera, 1536-point FFT for 3GPP long term evolution, Tech. Rep, p.480, 2007.

. Sheng-yeng, . Kai-ting, and Y. Chao-ming, Energy-efficient 128&#x223C;2048/1536-point FFT processor with resource block mapping for 3GPP-LTE system, The 2010 International Conference on Green Circuits and Systems, pp.14-17, 2010.
DOI : 10.1109/ICGCS.2010.5543106

J. Cooley and J. Tukey, An algorithm for the machine calculation of complex Fourier series, Mathematics of Computation, vol.19, issue.90, pp.297-301, 1965.
DOI : 10.1090/S0025-5718-1965-0178586-1

S. Winograd, On computing the Discrete Fourier Transform, Proceedings of the National Academy of Sciences, vol.73, issue.4, pp.175-199, 1978.
DOI : 10.1073/pnas.73.4.1005

J. V. Newmann, First Draft of a Report on the EDVAC, Tech. Rep, 1945.
DOI : 10.1007/978-3-642-61812-3_30

T. Finley, Two's complement, Cornell University lecture notes, 2000.

H. Liu and H. Lee, A high performance four-parallel 128/64-point radix-2 4 FFT/IFFT processor for MIMO-OFDM systems, Proc. IEEE Asia-Pacific Conf. Circuits Syst, pp.834-837, 2008.

O. Gustafsson, A. G. Dempster, K. Johansson, M. D. Macleod, and L. Wanhammar, Simplified Design of Constant Coefficient Multipliers, Circuits, Systems and Signal Processing, pp.225-251, 2006.
DOI : 10.1007/s00034-005-2505-5

J. Thong and N. Nicolici, Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.17, issue.9, pp.1353-1357, 2009.
DOI : 10.1109/TVLSI.2008.2003004

M. Garrido, F. Qureshi, and O. Gustafsson, Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI), IEEE Transactions on Circuits and Systems I: Regular Papers, vol.61, issue.7, pp.2002-2012, 2014.
DOI : 10.1109/TCSI.2014.2304664

URL : http://liu.diva-portal.org/smash/get/diva2:738039/FULLTEXT01

W. L. Constantinides, Y. K. Peter, and . Cheung, Synthesis and optimization of DSP algorithms, 2004.