H. Shibata, R. Schreier, W. Yang, A. Shaikh, D. Paterson et al., A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f0 = 450 MHz Using 550 mW, IEEE Journal of Solid-State Circuits, vol.47, issue.12, pp.2888-2897, 2012.

R. Zanbaghi, P. K. Hanumolu, and T. S. Fiez, An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT Delta Sigma Modulator Dissipating 13.7-mW, IEEE Journal of Solid-State Circuits, vol.48, issue.2, pp.487-501, 2013.

H. Chae and M. P. Flynn, A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability, IEEE Journal of Solid-State Circuits, vol.51, issue.3, pp.649-659, 2016.

H. Chae, J. Jeong, G. Manganaro, and M. P. Flynn, A 12 mW Low Power Continuous-Time Bandpass delta sigma Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF, IEEE Journal of SolidState Circuits, vol.49, issue.2, pp.405-415, 2014.

A. Edward, Q. Liu, C. Briseno-vidrios, M. Kinyua, E. G. Soenen et al., A 43-mW MASH 2-2 CT SigmaDelta Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS, IEEE Journal of Solid-State Circuits, vol.52, issue.2, pp.448-459, 2017.

X. Yang and H. Lee, Design of a 4th-order multi-stage feedforward operational amplifier for continuous-time bandpass delta sigma modulators, 2016 IEEE Int. Symp. on Circuits and Systems (ISCAS), pp.1058-1061, 2016.

P. G. Jespers and B. Murmann, Systematic design of analog CMOS circuits using pre-computed lookup tables. Cambridge, 2017.

L. Luh, J. Choma, and J. Draper, A continuous-time common-mode feedback circuit (CMFB) for high-impedance current mode application, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196), vol.3, pp.347-350, 1998.