This work presents a methodology for sizing transistors of a multi-stage, multi-path capacitor-less feed-forward compensated operational amplifiers employed in advanced CMOS process implementation of continuous-time bandpass Σ∆-modulators. The paper describes the methodology: on system level, dealing with the placement of poles and zeros; and on circuit level, discussing issues related to biasing, frequency response and other important performance metrics of the basic diff-pair. Algorithms are provided to simplify mathematical aspects of the work. The validity and the limitations of the proposed methodology are further discussed from the single-pole system used to model the individual amplification stages of the multi-stage amplifier. The worthiness of the proposed methodology in sizing the transistors of complex amplifier structures such as the capacitor-less multi-stage, multi-path feed-forward-compensated amplifiers is demonstrated using two design examples. A 3 rd-order amplifier with a DC gain of 52.6 dB and that reaches a unity-gain frequency of above 14 GHz while consuming only 5.6 mA from a 1 V supply; and a 4 th-order amplifier with DC gain of 73.5 dB that achieves a 25.7 dB gain at 1 GHz while consuming 4.8 mW are designed in 28nm CMOS FDSOI.