Distributed clock generator for synchronous SoC using ADPLL network

Abstract : This paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating synchronously in a frequency range of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation offers flexibility and efficient synchronization control suitable for use in synchronous SoCs.
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Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, et al.. Distributed clock generator for synchronous SoC using ADPLL network. CICC 2013 - IEEE 2013 Custom Integrated Circuits Conference, Sep 2013, San José, CA, United States. pp.1-4, ⟨10.1109/CICC.2013.6658437⟩. ⟨hal-01053768⟩

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