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Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design

Abstract : The design methodology of an embedded system should start with a system-level partitioning dividing functions into hardware and software. However, since this partitioning decision is taken at a high level of abstraction, we propose regularly validating the selected partitioning during software development. The paper introduces a new model-based engineering process with a supporting toolkit, first performing system-level partitioning, and then assessing the partitioning choices thus obtained at different levels of abstraction during software design. This assessment shall in particular validate the assumptions made on system-level (e.g. on cache miss rates) that cannot be precisely determined without low-level hardware model. High-level partitioning simulations/verification rely on custom model-checkers and abstract models of software and hardware, while low-level prototyping simulations rely on automatically generated C-POSIX software code executing on a cycle-precise virtual prototyping platform. An automotive case study on an automatic braking applicationillustrates our complete approach.
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Submitted on : Thursday, February 23, 2017 - 2:13:31 PM
Last modification on : Sunday, June 26, 2022 - 9:44:08 AM
Long-term archiving on: : Wednesday, May 24, 2017 - 1:46:01 PM


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  • HAL Id : hal-01447148, version 1


Daniela Genius, Letitia Li, Ludovic Apvrille. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design . 5th International Conference on Model-Driven Engineering and Software Development (MODELSWARD 2017), INSTICC, Feb 2017, Porto, Portugal. ⟨hal-01447148⟩



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