This paper presents the design and implementation of second generation current conveyor CCII- in 0.35μm CMOS process. In the design, we intended to achieve very low output impedance of voltage buffer over wide frequency range, in order to comply with high requirements for laboratory instrumentation. Selected approach relies on the optimization of voltage buffer, which is composed of minimal amount of transistors. This allows considerably reducing all parasitic capacitances in the circuit and achieving very low output impedance in units of ohms at frequencies up to 10 MHz. In addition, the solution exhibits high driving capability of both X and Z output terminals.