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Swimming pool like distributed architecture for clock generation in large many-core SoC

Abstract : —Synchronization is an issue of significant impor-tance in large-scale, distributed and high-speed systems. Tradi-tional globally synchronous approach is no longer viable due to severe wire delay. Solutions such as "Globally Asynchronous, Lo-cally Synchronous (GALS)" approaches suffer from metastability risk limiting their use in many-core SoC for critical applications, such as aerospace, military or medical equipment. This paper presents a distributed clock generator based on a network of oscillators. A great advantage of this architecture is its high stability and immunity to perturbations. This architecture also makes possible to design large fully synchronous SoC. A 10×10 network supplying clock sources for 100 clock domains has been modeled in VHDL and is under design in silicon. Simulation results show ± 40 ps peak-to-peak phase error between two neighboring clock signals and ± 50 ps between two clocks in distance.
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Contributor : Chuan Shan <>
Submitted on : Tuesday, November 4, 2014 - 1:16:25 PM
Last modification on : Friday, January 8, 2021 - 5:32:07 PM
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Chuan Shan, François Anceau, Dimitri Galayko, Eldar Zianbetov. Swimming pool like distributed architecture for clock generation in large many-core SoC. International Symposium on Circuits and Systemss, 2014, Jun 2014, Melbourne, Australia. pp.2768 - 2771, ⟨10.1109/ISCAS.2014.6865747⟩. ⟨hal-01080071⟩



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