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Conference Papers Year : 2012

The Effect of S-box Design on Pipelined AES Using FPGAs

Abstract

This work discuses the difference between three methods are used to implement S-box stage of AES. BRAM, composite field, and ROM are these methods. The comparison is based on FPGA implementation of these methods.

Keywords

Applied cryptography

Domains

Hardware Architecture [cs.AR]

Roselyne Chotin  : Connect in order to contact the contributor

https://hal.sorbonne-universite.fr/hal-01265624

Submitted on : Monday, February 1, 2016-1:41:42 PM

Last modification on : Tuesday, April 11, 2023-3:16:28 PM

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Dates and versions

hal-01265624 , version 1 (01-02-2016)

Identifiers

  • HAL Id : hal-01265624 , version 1

Cite

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. The Effect of S-box Design on Pipelined AES Using FPGAs. Colloque GDR SOC-SIP, Jun 2012, Paris, France. pp.1-4. ⟨hal-01265624⟩

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