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Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA

Umer Farooq 1, * M. Faisal Aslam 2
* Corresponding author
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : Over the past few years, cryptographic algorithms have become increasingly important. Advanced Encryption Standard (AES) algorithm was introduced in early 2000. It is widely adopted because of its easy implementation and robust security. In this work, AES is implemented on FPGA using five different techniques. These techniques are based on optimized implementation of AES on FPGA by making efficient resource usage of the target device. Experimental results obtained are quite varying in nature. They range from smallest (suitable for area critical application) to fastest (suitable for performance critical applications) implementation. Finally, technique making efficient usage of resources leads to frequency of 886.64 MHz and throughput of 113.5 Gb/s with moderate resource consumption on a Spartan-6 device. Furthermore, comparison between proposed technique and existing work shows that our technique has 32% higher frequency, while consuming 2.63Â more slice LUTs, 8.33Â less slice registers, and 12.59Â less LUT-FF pairs.
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Umer Farooq, M. Faisal Aslam. Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA. Journal of King Saud University - Computer and Information Sciences, Elsevier 2016, ⟨10.1016/j.jksuci.2016.01.004⟩. ⟨hal-01298000⟩

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