Modular on chip multi processor for routing applications
Abstract
Simulation platforms for network processing still have difficulties in finding a good compromise betweenspeed and accuracy.This makes it difficult to identify the causes of performance bottlenecks: Are they caused by application, hardware architecture, or by a specificity of the operating system? We propose a simulation methodology for a multiprocessor network processing platform which contains sufficient detail to permit very precise simulation and performance evaluation whilestaying within reasonable limits of both specification and simulation time. As a case study, we show how a model can be developed for a IPv4 packet routing application, exhibiting the performance and scalability bottlenecks and can thus be used to reason about architectural alternatives.
Domains
Computer Science [cs]
Origin : Files produced by the author(s)
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