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A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA

Mohammed Shaaban Ibraheem 1 Syed Zahid Ahmed 1 Khalil Hachicha 1 Patrick Garda 1 
1 SYEL - Systèmes Electroniques
LIP6 - Laboratoire d'Informatique de Paris 6
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https://hal.sorbonne-universite.fr/hal-01440500
Contributor : Mohammed IBRAHEEM Connect in order to contact the contributor
Submitted on : Thursday, January 19, 2017 - 12:10:59 PM
Last modification on : Sunday, June 26, 2022 - 9:46:07 AM

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Mohammed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha, Patrick Garda. A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA. FPGA '16 Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Feb 2016, Monterey, California, United States. ⟨10.1145/2847263.2847321⟩. ⟨hal-01440500⟩

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