Along with performance, one of the main concerns in cryptographer circuits implementation is Side Channel Attacks robustness. Given a cipher, many functionally equivalent circuits can be associated, with mixed performances and robustness. The work presented in this paper consists in a methodological effort to assist and qualify cipher circuits designs with a framework for a modular, sustained and iterative workflow through know-how capitalization. Simulation allows qualifying cipher hardware implementations against threats such as physical cryptanalysis. New versions are to be compared with respect to references early in design workflow, judging counter-measure efficiency or preventing security regressions.