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Conference papers
Design and Modeling of ADPLL with sliding-window for wide range frequency tracking
Abstract : An architecture of All-Digital Phase-Locked Loop (ADPLL) with sliding window for wide range frequency tracking is proposed to reduce energy consumption and to accelerate convergence. A synthesizable VHDL model is created for this circuit. Simulation and syntheses results demonstrate high performance of the new architecture.
Cited literature [8 references]
https://hal.sorbonne-universite.fr/hal-01053756
Contributor : Chuan Shan <>
Submitted on : Monday, August 4, 2014 - 2:42:11 PM
Last modification on : Friday, January 8, 2021 - 5:32:07 PM
Long-term archiving on: : Tuesday, November 25, 2014 - 11:21:10 PM
Contributor : Chuan Shan <>
Submitted on : Monday, August 4, 2014 - 2:42:11 PM
Last modification on : Friday, January 8, 2021 - 5:32:07 PM
Long-term archiving on: : Tuesday, November 25, 2014 - 11:21:10 PM
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NEWCAS2012-5.pdf
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