FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation

Chuan Shan 1 Eldar Zianbetov 1 Weiqiang Yu 2 François Anceau 1 Olivier Billoint 3 Dimitri Galayko 1
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
2 LIP - Laboratoire de l'Informatique du Parallélisme
3 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information
Abstract : In this paper, we present an FPGA modelling of a distributed and synchronized clock generation for different clock domains based on coupled all-digital phase locked loops (ADPLLs). An implementation of a programmable and reconfigurable 10 ×10 ADPLL network is described, designed for prototyping distributed clock generation in large synchronous system on chip (SoC). The paper emphasizes the reconfigurability of proposed system, which allows exploiting stability issues and nonlinear behavior of a N × M network of coupled oscillators (the dimension can be configured from 1 × 1 to 10 × 10). Configurations with different parameters are compared and analyzed. A dynamic setup mechanism is proposed, allowing selecting the desired synchronized state. Experimental results validate theoretical analysis about circuit parameters and demonstrate the global synchronization of network and performance for different configurations.
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Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, et al.. FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, Dec 2013, Cancun, Mexico. pp.1 - 6, ⟨10.1109/ReConFig.2013.6732295⟩. ⟨hal-01053762⟩

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